Position3:
Engineer (Wafer Prep)
Location:
Serangoon North

Emp Type
Full Time



   Responsibilities
.
Support engineering build related to new packaging / process for customer sampling or internal evaluations.
Provide support in documentation for process control during technology offload to assembly.
Run evaluations per plan and collect necessary data for analysis.
Liaise with suppliers to identify improvements required on equipment or materials.

   Requirements
.
At least 3 years' experience in IC assembly companies, in Front-Of-Line (FOL).
Degree in Engineering or equivalent.
Good problem solving, communication and presentation skills
Knowledge of Statistical Process Control (SPC) and Design of Experiments (DOE)

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Position5:
Engineer (Technology Proliferation and Pathfinding Resources)
Location:
Serangoon North,Singapore

Emp Type
Full Time



   Responsibilities
.
Technical assessment on new material that has no baseline evaluated before, or no-known capability in Assembly
Co-work with process / design / simulation groups to address issues based on materials technicality.
Define new materials critical buy-off criteria & special properties procurement specifications
Improve material selection & qualification efficiency by partnering with suppliers via collaborations
Perform risk management approach for new DM implementation (i.e. product readiness, cost, MOQ, HVM stability)
Improved time to market with stable and readily available suitable material

   Requirements
.
Min working experience in semiconductor or related field for 3-5 years.
Bachelors degree in Materials related Course (Chemical Engg, Materials Science, Metallurgy Engg)
Exposure at EOL process and with good baseline understanding on mold materials.
Good demonstration in interpersonal relationship.
Able to work under a fast pace working environment.

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Position4:
Senior/Engineer (Flip Chip)
Location:
Serangoon North
Emp Type:
Full Time


   Responsibilities
.
To be involved in the next generation advanced packaging and technology development for UTAC specifically in the area of Advanced Flip Chip Packages.
Develop/Enhance current/new assembly process and materials focusing on single/multi-stacked Hybrid flip chip die bonding & Underfill processes. Advanced 40/32/28nm Flip chip ELK technology development.
Work closely with equipment vendors and local research institute for new and advanced assembly processes.
Provide expert opinions and problem resolutions on assembly issues
Promote UTAC excellence via external technical presentations and publications.

   Requirements
.
PhD/ Masters/ Degree in Engineering with minimum 3-5 year’s experience in IC packaging, specifically in Flip-Chip Assembly.
Min 2-3 years of Process Development experience in 1 or more of the following processes: Flip Chip Attach/Reflow, Unerfill Dispense, HS/SR Attach or Flux Cleaning is required
Prior research experiences in 40/32/28nm ELK Technology, NCP, No-flow UF, pre-applied or wafer-level UF will be an added advantage.
Innovative, creative and resourceful.
A team player, but at the same time independent and proactive.
Good communication & interpersonal skills. Able to work well with peers and management.
Willing to learn, work hard, and experiment new things. Like challenges of the unknown.

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